There is known a clock transfer circuit having a serial shift register which serially writes reception data in accordance with a write clock of n-th power (n≠0) of 2 of a transfer clock, and outputs the data in parallel (refer to Patent Document 1). A clock generator generates the write clock and the transfer clock for transferring the reception data. A deviation detecting unit detects a deviation of phase difference between a reception and reproduction clock generated based on the reception data and the transfer clock. A selection circuit determines, based on the deviation of the phase difference detected by the deviation detecting unit, a selection position of data selected from a data sequence output from the serial shift register. A flip-flop outputs the data selected by the selection circuit in synchronization with the transfer clock. The clock transfer circuit transfers the reception data by transferring the data onto a stable clock.
Further, there is known a synchronization correction circuit of a loop transmitter in which it is designed such that each station individually generates a transmission clock with the same frequency, and a relay operation is conducted by converting a reception signal into a transmission signal in synchronization with the transmission clock (refer to Patent Document 2). A variable delay circuit delays the reception signal for a variable period of time. A phase difference detecting circuit detects a phase difference between an output of the variable delay circuit and the transmission clock. A setting unit sets the variable period of time of the variable delay circuit based on the phase difference.
Further, there is known a clock phase adjusting circuit used when acquiring input data of a predetermined cycle in accordance with a timing of a clock signal of a cycle same as the predetermined cycle (refer to Patent Document 3). A phase control unit controls a phase of the clock signal in accordance with a control signal. An out-of-synchronization detecting unit detects, based on a clock signal after being subjected to the phase adjustment by the phase control unit and the input data, an out-of-synchronization state of the input data with respect to the phase-adjusted clock signal. A pulse generating unit generates pulses at regular periods, during a period of time in which the out-of-synchronization state is detected by the out-of-synchronization detecting unit. A control signal generating unit generates a control signal in accordance with a number of generation of the pulses.
Patent Document 1: Japanese Laid-open Patent Publication No. 10-190639
Patent Document 2: Japanese Laid-open Patent Publication No. 61-245731
Patent Document 3: Japanese Laid-open Patent Publication No. 09-149015
A jitter is a fluctuation of phase in a time axis direction of a digital signal. In particular, a low-frequency jitter is called as wander. If a first-in-first-out (FIFO) circuit for performing buffering of data is used for absorbing the wander of clock signal, a configuration for performing a write control and a read control of the FIFO circuit becomes complicated, resulting in that an area of the entire integrated circuit is increased.